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AMD-756 peripheral bus controller revision guide publication # 22591 rev: c issue date: may 2000 version created may 11, 2000 tm preliminary information
trademarks amd, the amd logo, and combinations thereof, amd athlon, amd-751, and AMD-756 are trademarks of advanced micro devices, inc. microsoft, windows, and windows nt are registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2000 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the amd products described herein may contain design defects or errors (?product errata?) that causes the amd products to deviate from published specifications. currently characterized product errata may be available upon request. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
1 22591c/0?may 2000 AMD-756? peripheral bus controller revision guide preliminary information AMD-756? peripheral bus controller revision guide the purpose of the AMD-756? peripheral bus controller revision guide is to communicate updated product information on the AMD-756 peripheral bus controller to designers of computer systems and software developers. this guide consists of three major sections: product marking identification: this section, which starts on page 2, provides product types, product revisions, opns (ordering part numbers), and product marking information. product errata: this section, which starts on page 3, provides a detailed description of product errata, including potential effects on system operation and suggested workarounds. an errata is defined as a deviation from the product ? s specification. a product errata may cause the behavior of the AMD-756 peripheral bus controller to deviate from the published specifications. product enhancements: this section, which starts on page 11, provides a description of product enhancements. revision determination: this section starts on page 12. technical and documentation support: this section, which starts on page 13, provides a listing of available technical support resources. it also lists corrections, modifications, and clarifications to listed documents. revision guide policy occasionally, amd identifies deviations from or changes to the specification of the AMD-756 peripheral bus controller. these changes are documented in the AMD-756 ? peripheral bus controller revision guide as errata. descriptions are written to assist system and software designers in using the AMD-756 controller, and corrections to amd ? s documentation on the AMD-756 controller are included. this release documents currently characterized product errata.
2 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information 1 product marking identification AMD-756 tm AMD-756ac b date code amd 1998 c product revision family/core AMD-756 package type a = plastic ball grid array c = commercial temperature range case temperature table 1. valid ordering part number (opn) combinations opn package type operating voltage case temperature AMD-756 272-pin bga 3.0 v?3.6 v 70 c notes: valid combinations are configurations that are planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations.
3 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information 2 product errata this section documents AMD-756 peripheral bus controller product errata. the errata are divided into categories to assist referencing particular errata. a unique tracking number for each errata has been assigned within this document for user convenience in tracking the errata within specific revision levels. table 2 cross-references the revisions of the AMD-756 peripheral bus controller to each errata number. an ? x ? indicates that the errata applies to the stepping. the absence of an ? x ? indicates that the errata does not apply to the stepping. note: there can be missing errata numbers. errata that have been resolved from early revisions of the controller have been deleted, and errata that have been reconsidered may have been deleted or renumbered. table 2. cross-reference of product revision to errata errata number and description revision number d2 d4 ide controller 1 obsolete single-word dma mode not supported x usb controller 4 usb controller will occasionally not enumerate slow-speed devices x 10 usb devices occasionally will not wake system while in suspend mode xx 11 usb register documentation error xx 12 usb register documentation clarification xx pci 6 pci revision documentation xx 7 pci input hold time violation xx 8 pci target abort decode error x 13 pci bus parking while a cycle is taking place xx 14 target-driven pci data bus after pci turnaround cycle xx 15 pci special cycles being delayed xx sm bus 9 system management (sm) bus-busy bit not set immediately x
4 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information ide controller 1 obsolete single-word dma mode not supported products affected. d2 normal specified operation. for a very limited number of old ide devices, single-word dma mode is supported. this mode is not allowed within the current ata specification. variance. the AMD-756 peripheral bus controller does not support the obsolete single-word dma mode. potential effect on system. system hang. suggested workaround. udma-capable devices are not affected. use the amd-supplied eide driver with windows ? 95, windows 98, and windows nt ? 4.0. bios vendors have been notified that the dma- capable bit in the bus mastering status register of the ide controller must be set to 0 for any hard drive whose highest performance transfer mode is multi-word dma. resolution status. fixed in revision d4.
5 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information usb controller 4 usb controller will occasionally not enumerate slow-speed devices products affected. d2 normal specified operation. whenever a usb device is initialized, it should be detected by the usb host controller in the AMD-756 peripheral bus controller. non-conformance. when the AMD-756 peripheral bus controller is performing usb-initiated pci master cycles and a usb device is initialized, it may not be detected correctly. during this time, data corruption occurs in usb status registers located at offset locations 34h and above. this behavior only exists for low-speed devices. this behavior is seen in the following two cases: slow-speed devices are occasionally not detected at boot time. slow-speed devices are occasionally not detected when hot plugged. potential effect on system. usb devices are occasionally not detected by the host controller. suggested workaround. update the bios according to the bios supplier ? s directions. if bios update is unavailable, restart the machine to reinitialize usb detection. install a new microsoft ? usb driver openhci.sys. the microsoft knowledge base number for the microsoft driver that reduces the failure rate for the AMD-756 usb enumeration issue to a minimal level is q241134. the microsoft description of the driver fix is available at the following url: http://support.microsoft.com/support/kb/articles/q241/1/34.asp if this driver is unavailable, unplugging and reconnecting the usb devices or rebooting allows the correct usb device enumeration. for more information, see the AMD-756 peripheral bus controller usb initialization application note , order number 90017. resolution status. fixed in revision d4
6 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information 10 usb devices occasionally will not wake system while in suspend mode products affected. d2, d4 normal specified operation. whenever a usb device is disconnected from the system it should be detected by the usb host controller in the AMD-756 peripheral bus controller. non-conformance. when the platform is placed into low-power standby mode the AMD-756 peripheral bus controller should always detect the removal of a usb device and awake the system to full-on mode. occasionally when a usb device is removed from the platform, usb signal bounce is not debounced correctly in the AMD-756. this results in the following registers not being updated correctly. usb status registers located at offset locations 54, 58, 5c, and 60, bit 0, currentconnectstatus will show the device connected. usb status registers located at offset locations 54, 58, 5c, and 60, bit 16, connectstatuschange will show no connect/disconnect event. potential effect on system. removal of usb devices may not wake system from standby mode. suggested workaround. the following methods will return the system to full-on mode. use power button to wake the system and place in full-on mode. connect the usb device to a different usb port. resolution status. no fix planned. 11 usb register documentation error products affected. all documentation errata. on page 282 of the AMD-756 peripheral bus controller data sheet (order number 22548b), the access types for bit 9 (low-speed device attached) and bit 8 (port power status) of the hcrh port 1 status register are incorrectly defined. both bits should be defined as read-only. potential effect on system. none, the AMD-756 peripheral bus controller does not support external usb power switching. suggested workaround. none . resolution status. no fix planned. 12 usb register documentation clarification products affected. all documentation clarification. on page 283 of the AMD-756 peripheral bus controller data sheet (order number 22548b), bit 1 (pes) and bit 0 (ccs) of the hcrh port 1 status register are defined as rwc. these two bits work together to allow setting and clearing of the portenablestatus bit (pes). writing a 1b to bit 1 (pes) sets portenablestatus. writing a 1b to bit 0 (ccs) clears portenablestatus. writing a 0b to either of these bits has no effect. reading bit 0 returns ccs. reading bit 1 returns pes. resolution status. no fix planned.
7 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information pci 6 pci revision documentation products affected. all normal specified operation. bios checks pci revision id register for function 0 at offset 8 to determine version of silicon . non-conformance. previous metal-only updates to the AMD-756 peripheral bus controller have resulted in not updating the function 0 id register. the revision id updates have been performed in function 1 and function 3 configuration spaces. table 3 shows the AMD-756 peripheral bus controller revision version values. the column titled sequence shows the progressive linear increments of the AMD-756 peripheral bus controller. all functions added in a previous sequence are included in the next sequence. potential effect on system. none. suggested workaround. bios algorithm needs to check function 1 and function 3 for proper device id. resolution status. no fix is planned. 7 pci input hold time violation products affected. all normal specified operation. hold time for pci inputs is specified as 0 ns in pci 2.2 specification. non-conformance. the AMD-756 peripheral bus controller pci input hold time is specified at 1 ns. potential effect on system. none, because all pci products hold data at their inputs for at least 2 ns. suggested workaround. none . resolution status. no fix planned. table 3. AMD-756? peripheral bus controller revision ids sequence revision function 1 offset 8 function 3 offset 8 1d1 31 2d2 33 3d3 63 4d4 73 5 reserved 83 6 reserved 93
8 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information 8 pci target abort decode error products affected. d2 normal specified operation. pci devices may terminate a transfer with a target abort cycle. non-conformance. the AMD-756 peripheral bus controller does not detect target abort cycles correctly and will subtractively decode such cycles. this results in the AMD-756 controller asserting devsel# for an extended period of time. the target abort cycle is a catastrophic device failure and should not occur in the majority of existing pci devices. potential effect on system. system locking with windows nt ? server version 4.0 and windows 2000. suggested workaround. obtain bios or driver updates from the manufacturer of any pci device that performs target aborts to eliminate this behavior. contact your amd representative for further information. resolution status. fixed in revision d4. 13 pci bus parking while a cycle is taking place products affected. all normal specified operation. the AMD-756 peripheral bus controller must not drive pci c/be# lines while entering pci bus park mode. non-conformance. if the northbridge parks the pci bus on the AMD-756 peripheral bus controller while the northbridge is executing a pci cycle, the AMD-756 will drive the c/be# lines for one pci clock. potential effect on system. none. the amd northbridge should always park on itself (default). suggested workaround. none. resolution status. no fix planned. 14 target-driven pci data bus after pci turnaround cycle products affected. all normal specified operation. the target of a pci read cycle drives the pci data bus after the turnaround cycle has completed. this is to limit the amount of time that the pci address and data bus floats. non-conformance. when the AMD-756 peripheral bus controller is a target for a pci read cycle, the AMD-756 does not drive the pci data bus until it is ready to supply the data. potential effect on system. none. suggested workaround. none. resolution status. no fix planned.
9 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information 15 pci special cycles being delayed products affected. all normal specified operation. whenever a pci special cycle is directed to the AMD-756 peripheral bus controller, the data phase can be delayed by 16 pci clocks after assertion of frame# control signal. non-conformance. when a pci special cycle is directed to the AMD-756 the data phase must be valid by the third pci clock after the assertion of frame# control signal. if the pci data is delayed longer than three pci clocks past assertion of frame#, the AMD-756 will respond improperly. potential effect on system. none. the amd-751 system controller (northbridge) always presents valid data for pci special cycle two pci clocks after assertion of frame#. suggested workaround. none. resolution status. no fix planned.
10 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information sm bus 9 system management (sm) bus-busy bit not set immediately products affected. d2 normal specified operation. the AMD-756 peripheral bus controller should set the busy bit located at function 3 offset pme0: smbus global status register bit [smb_bsy] immediately after the start command is issued by software setting the host start bit. non-conformance. the AMD-756 peripheral bus controller sets the busy bit pme0[smb_bsy] only after software sets the host start bit and the sm bus cycle has started. the smbus host start bit is located at function 3 offset pme2: smbus global control register bit [hostst]. potential effect on system. if a new address is written between the time the start command is written and the time the sm bus cycle begins, some sm bus cycles may be redirected to another address. suggested workaround. software can read and check for non-zero status of the following bits to guarantee cycle completion before starting a new cycle. see the system management busy bit application note for more information. function 3 offset pme0: smbus global status register pme0[to_sts] time out error status pme0[hcyc_sts] host cycle complete status pme0[perr_sts] protocol error status pme0[col_sts] host collision status resolution status. fixed in revision d4.
11 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information 3 product enhancements revision d4 enhancements century byte implementation on the AMD-756? peripheral bus controller, revision d4 the AMD-756 peripheral bus controller revision d4 supports the following new features, which can be used for century byte patch: port 70h was previously write-only but the content can now be read from c3a5c[15:8]. c3a5c[15:8] bits store the last value written to port 70h, including the nmi enable. an smi can be generated when the century byte cmos 7fh rolls over. c3a5c[7] = century byte rollover smi enable bit. once this bit is set, smi is generated when status bit pm28[13] is set. pm28[13] = century byte rollover status bit. this bit is set when cmos 7fh rolls over. the AMD-756 peripheral bus controller revision d4 has the ability to generate an smi when the century byte rollover occurs. this can be used to update the cmos century locations. in revision d4, the century byte rollover smi enable was added at register c3a5c[ncsmi_en]. when a century change occurs, the register pm28[newcen_sts] is set and the century field at rtc cmos offset 7fh increments. the ability to read the last byte written to port 70h was added to c3a5c[rtcaddr], so that this state can be restored to port 70h after the century byte smi routine finishes updating rtc cmos 32h. the rollover smi patch is described in the ? century byte diagnostics ? section of the AMD-756 ? peripheral bus controller century byte programming application note , order number 90001. this method takes advantage of the new d4 features.
12 AMD-756 ? peripheral bus controller revision guide 22591c/0 ? may 2000 preliminary information 4 revision determination refer to errata number 6 pci revision documentation on page 7 for details regarding the AMD-756 peripheral bus controller revision identification.
13 22591c/0 ? may 2000 AMD-756 ? peripheral bus controller revision guide preliminary information 5 technical and documentation support 5.1 documentation support the following documents provide additional information regarding the operation of the AMD-756 peripheral bus controller: amd-751 ? system controller data sheet (order# 21910) AMD-756 ? peripheral bus controller data sheet (order# 22548) amd athlon ? system bus specification (order# 21902) amd athlon ? processor bios, software, and debug tools developers guide (order# 21656) amd athlon ? processor data sheet (order# 21016) for the latest updates, refer to www.amd.com and download the appropriate files. for documents under nda, please contact your local sales representative for updates.

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